1. Field of the Invention
The present invention relates to a circuit device and a manufacturing method thereof.
2. Description of the Related Art
With an accelerated advance in higher function portable electronics devices such as portable telephones, PDAs, DVCs and DSCs, in order that such products may be accepted by the market, smaller size and lighter weight are indispensable; accordingly, in order to realize this, highly integrated system LSIs are in demand. On the other hand, on such electronics devices, more easy-to-use and convenient ones are demanded; accordingly, on LSIs that are used in devices, higher function and higher performance are demanded. Accordingly, as an LSI chip is highly integrated, the number of I/O increases on the one hand; on the other hand a demand on miniaturization of a package itself is strong. In order to combine these, a development of a semiconductor package suitable for dense substrate mounting of semiconductor elements is strong in demand. In order to cope with such demands, a packaging technology called a CSP (Chip Size Package) is variously developed.
As an example of such a package, a BGA (Ball Grid Array) is known. The BGA is formed by mounting a semiconductor chip on a packaging substrate, followed by applying resin molding thereto, further followed by forming solder balls in area on an opposite surface as external terminals. In the BGA, a mounting area is achieved in area; accordingly, a package can be relatively easily miniaturized. Furthermore, there is no need of coping with the narrow pitch on a circuit board side and precise mounting technology becomes unnecessary; accordingly, when the BGA is used, even in the case where the package cost is a little bit higher, the mounting cost can be reduced as a whole.
FIG. 4 is a diagram showing a schematic configuration of a general BGA. A BGA 100 has a structure in which on a glass epoxy substrate 106, an LSI chip 102 is mounted through an adhesive layer 108. The LSI chip 102 is molded with a sealing resin 110. The LSI chip 102 and the glass epoxy substrate 106 are electrically connected with metal wires 104. On a back face of the glass epoxy substrate 106, solder balls 112 are arranged in array. Through the solder balls 112, the BGA 100 is mounted on a printed circuit board.
In such a package, when a semiconductor chip is sealed, for instance, transfer molding, injection molding, potting, dipping or the like is used (for instance, refer to Japanese Patent Laid-Open No. 08-162486).
Furthermore, in order to realize more precise, higher function and thinner LSIs, a technology in which on an upper portion of a base substrate, by means of a thin film technology or a thick film technology, a layer that includes a passive element that is made of a resistive element portion, a capacitor portion or a pattern wiring portion that receive power or signal supply from a base substrate side through a dielectric insulating layer is formed is disclosed (for instance, Japanese Patent Laid-Open No. 2002-94247).
However, in the existing CSPs such as disclosed in Japanese Patent Laid-Open No. 08-162486, smaller size, smaller thickness and lighter weight to an extent that is desired at present in the portable electronics devices cannot be realized. Furthermore, in an improvement in the heat dissipation properties, there is a definite limit.
Furthermore, in the technology such as disclosed in Japanese Patent Laid-Open No. 2002-94247 where a layer including a passive element made of a resistive element portion, a capacitor portion or a pattern wiring portion is formed, as a thin film or thick film formation process, a very complicated process is used; accordingly, there is a room for a further improvement in the manufacturing cost of the passive element. Still furthermore, in such a complicated process, a surface of the passive element can be flattened with difficulty; accordingly, there is a room for a further improvement in the manufacturing stability.